Modern integrated circuits incorporate a variety of design-for-test (DFT) structures to enhance their inherent testability. The most popular DFT structure is based on scan design where a plurality of externally accessible scan chains are embedded into the integrated circuit. Each scan chain includes one or more scan cells coupled in series, with each scan cell comprising a scan flip-flop or a scan latch. Typically, scan design is used in conjunction with fault simulation and combinational ATPG (automatic test pattern generation) to generate manufacturing and diagnostic test patterns for production test, prototype debug, and yield improvement.
The increasing scale of integration has made it impractical to continue to implement scan designs where all scan chains are externally accessible, since the limited number of I/O pins results in a dramatic increase in the length of the scan chains which dramatically increases test cost. For these reasons, new DFT methodologies such as Logic BIST (built-in self-test) and Compressed Scan/ATPG have become increasingly popular. In these methodologies, scan chains are no longer externally accessible during the test process. Instead, a large number of scan chains are implemented in a design such that their scan chain inputs are controlled by pattern generators and their scan chain outputs are observed by pattern compactors. Pattern generators used include pseudorandom pattern generators (PRPG), random pattern generators (RPG), broadcasters, and decompressors. Pattern compactors used include multi-input signature-registers (MISRs) and linear compactors.
Utilizing these pattern generators and pattern compactors comes with the cost of limiting the amount of debug, diagnosis and yield-improvement possible using standard scan design techniques. In addition, unknown (‘x’) values generated by black-box circuits, or circuits where the capture results cannot be predicted by the automatic test pattern generation software, come with the additional cost of eliminating faults detected in other scan cells that are compacted alongside the scan cells capturing the unknown (‘x’) values. This lost fault coverage can dramatically lower the final fault coverage achieved.
Prior-art solutions to this problem fall under two categories. The first category of prior-art solutions focus on designing a mask network preceding the pattern compactor designed to prevent unknown (‘x’) values in the output scan data stream from reaching the pattern compactor. The second category of prior-art solutions focus on designing unknown (‘x’) tolerant compactors in order to limit the effect of unknown captured data on the fault coverage. There are inherent problems in each category of solutions. These prior-art solutions are summarized below:
Prior-art solution #1, FIG. 1A, is described in U.S. Pat. No. 6,557,129 by Rajski et al. (2003). This prior-art solution adds a selector circuit similar to what can be called an output-mask network, between the scan chain outputs and the inputs of the pattern compactor. A control circuit, similar to what can be called an output-mask controller is used to control which scan chains and scan cells should be prevented from being compacted in the pattern compactor. The main problem with this prior-art solution is that it is too general. Placing the output-mask network at the end of the scan chains and implementing a general output-mask controller requires a large amount of circuitry to mask off the required unknown values. Furthermore, placing the output-mask network between the outputs of the scan chains and the inputs of the pattern compactor reduces the speed at which the scan chains can be operated.
Prior-art solution #2, FIG. 1B, is described in papers by Mitra et al. (2002, 2003). In this solution, a design is proposed for an unknown (‘x’) tolerant pattern compactor capable of tolerating unknown (‘x’) values in the output scan data stream. The problem with this solution is that there is a limitation on the number of unknown (‘x’) bits that the unknown tolerant pattern compactor can tolerate, which depends on the compactor design. A further disadvantage as opposed to the first prior-art solution is that this solution cannot be used for debug and diagnosis of the scan chains after manufacturing.
Therefore, there is a need to improve upon the current unknown mask and tolerance capabilities of current solutions for DFT methodologies utilizing embedded scan chains. The solution according to this invention uses a small amount of circuitry for masking off unknown values in the output scan data stream from reaching the pattern compactors. In addition, this solution further allows one to perform scan debug, diagnosis and yield-improvement of the DFT methodologies utilizing embedded scan chains possibly without impacting the speed at which the scan operation is performed.